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As the size of integrated circuits shrinks, the development of process technology has encountered more and more technical bottlenecks in perforation, photolithography, tunneling, and heat dissipation. To continue to promote the improvement of chip performance, the world's leading semiconductor manufacturers have put forward different ideas, including innovating in terms of device structure, materials, and packaging. At this point, Chiplet began to move to the front of the stage and took on the big responsibility, but the challenge still lay. At the beginning of 2021, let us look back at Chiplet's ups and downs and its future journey.

In general, Chiplet technology is a new chip design method after SoC integration has developed to a certain level. It divides SoC into smaller dies (Die), and then interconnects these modular small chips (die). Together, using new packaging technology, small chips manufactured with different functions and different processes are packaged together to become a heterogeneous integrated chip.

The concept of Chiplet was proposed more than 10 years ago. Why has it become popular recently? Professor Yu Daquan, a Minjiang Scholar Distinguished Professor of Xiamen University, Ph GPU and memory can be classified as Chiplet category. In 2013, the FPGA jointly developed by TSMC and Xilinx is a typical case. As the development of Moore's Law slows down further, it is more and more difficult to upgrade the process, especially after entering the process of a few nanometers, only a few foundries can do it. In this case, the industry has high hopes for Chiplet technology. Chiplet heterogeneous integrated packaging is expected to solve the problem of chip performance cost caused by difficulty in process improvement.

It is precisely by using Chiplet technology that AMD EPYC processors have successfully implemented a high-performance server chip with integrated 64 cores. If the previous single chip design is used to integrate 64 cores, it is unrealistic and uneconomical under the existing technology. AMD is divided into small chips according to functional needs, and manufactured by using the best design process, not only can reduce costs, improve yield, and make multi-core and complex chip design possible. At the same time, modular design ideas can also increase the speed of chip development and reduce R&D costs.

Professor Yu Daquan said that the previous SoC chip design was the overall system design, but the current Chiplet technology can split a large chip such as a CPU into different functional modules according to their functions, design them separately, and manufacture them separately, and choose the appropriate package according to the needs. Technology for system integration, thus realizing the function of a system chip.

The electrical I/O standard defined by the Optical Interconnection Forum (OIF) shows that the data transmission rate is as high as 112Gbps on ultra-short-distance and extremely short-distance links (die-to-die interconnection). When designing the interconnection interface between the die and the die, the chip design company first guarantees high data throughput. In addition, data delay and bit error rate are also key requirements, and energy efficiency and link distance must also be considered.

In terms of interconnection, design vendors have their own unique tricks. Marvell uses the Kandou bus interface when launching the modular chip architecture; NVIDIA's high-speed interconnect NV Link solution for GPUs; Intel's freely authorized AIB advanced interface bus protocol; AMD's Infinity Fabrie bus interconnection technology, and HBM interfaces for stack interconnection of memory chips...These are different attempts by chip design companies to achieve high-speed interconnection.

Intel has made long-term investments in the road of heterogeneous interconnection. It launched EMIB technology many years ago, and recently launched Foveros3D stereo packaging technology. Unlike the past simply connecting logic chips and memory chips, Foveros can stack and connect different logic chips together, and can "mix and match" IP modules of different processes, architectures, and uses, as well as various memory and I/O units.